In a present technique of manufacturing transistors on a single die, by arranging stacked dies along a vertical direction, the dies with different functions or fabricated based on different techniques can be integrated, so as to resolve a difficulty of fabricating the transistors of different functions and different types on the single die. However, regarding a signal connecting layout in the stacked dies, a conventional technique is to change positions of bond pads through redistribution layer (RDL) routing at a front side or a back side of the die, and bond the stacked dies through micro bumps. By such means, the signal can be transmitted among the dies sequentially through the routing, the bond pads, the micro bumps and through silicon vias (TSVs).
Generally, the above connecting technique probably fixes a transmission mode of the signal among the stacked dies. Namely, if the signal transmission mode of the stacked dies is required to be changed, not only a layout of the micro bumps need to be changed, but also the RDL routing at the front side and the back side of the dies have to be totally changed, so as to cope with requirement of a new design. Further, redesigning of the RDL routing can increase a fabrication cost.